As the geometries for integrated circuits have scaled to smaller and smaller dimensions, it has become necessary to replace polysilicon transistor gates with metal gates to enable scaling to continue to smaller dimensions. When voltage is applied to a polysilicon gate the polysilicon grains next to the gate dielectric become depleted of carriers increasing the electrical thickness of the gate dielectric and exacerbating short channel effects. Metal gates do not deplete when voltage is applied to the metal gate.
Because the work function of most p-channel metal-oxide-semiconductor (PMOS) metal gate material changes when the metal gate is subjected to high temperatures such as is required to activate dopants, replacement gate processes have been developed to circumvent the work function problem. In a replacement gate process, transistors are first built in the usual manner using polysilicon gates and silicon dioxide gate dielectric. The polysilicon gates and gate dielectric are then removed and replaced with high-k gate dielectric and metal gates. Typically after removal of the polysilicon replacement gate, high-k dielectric is deposited followed by metal gate deposition. The high-k dielectric typically deposits conformally on the sidewalls and bottom of the trench formed by removal of the polysilicon replacement gate. Metal gate material is then deposited to fill the trench.
Because of the high dielectric constant of the high-k dielectric on the sidewalls of the trench, fringe capacitance is increased which degrades transistor performance.
In addition, gate geometries have been scaled to such small dimensions (i.e. less than 30 nm) that when the trench width is reduced by the high-k dielectric deposition, it is difficult to completely fill the trench without forming voids.